This application claims the benefit of Korean Patent Application No. 2000-319, filed Jan. 5, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to semiconductor memory devices and, more particularly, to sampling data contained in semiconductor memory devices.
The demand for semiconductor memory devices of increasing integration densities is generally increasing. As a result, the size of memory cell arrays may increase in both the word line and bit line dimensions. One potential problem with the increased size of memory cell arrays is that the speed with which data may be read may be different between those memory cells that are closer to the sense amplifiers and those memory cells that are farther away from the sense amplifiers.
A conventional semiconductor memory device typically includes a set of sense amplifiers that amplify and output data from a memory cell array in response to a sense amplifier enable signal. A set of data sampling circuits may also be included that sample respective pairs of output data from the sense amplifiers and pass the sampled data on to other circuitry for further processing in response to a sampling control signal. Typically, the timing of the sampling control signal is adjusted to allow the data sampling circuits to sample the sense amplifier output data that are associated with memory cells that are farthest away from the sense amplifiers. This is to ensure that the data sampling circuits do not attempt to sample the output data from the sense amplifiers too early before the data from memory cells more distant from the sense amplifiers is available. Thus, even though the speed at which data may be read from memory cells that are relatively far away from the sense amplifiers may be relatively slow, the data may nevertheless be sampled and passed on to other circuitry for further processing.
As the integration of semiconductor memory devices increases, however, the difference in the speed at which data is read from memory cells relatively far away from the sense amplifiers and the speed at which data is read from memory cells relatively close to the sense amplifiers may increase. As a result, conventional techniques for sampling data from a memory cell array may be inadequate.
In the same memory cell array block, the difference in speed at which data may be read may be more than 1 ns between memory cells that are relatively far away from the sense amplifiers and memory cells that are relatively close to the sense amplifiers. If the timing of the sampling control signal is adjusted to allow the data sampling circuits to sample the sense amplifier output data that are associated with memory cells that are farthest away from the sense amplifiers, then data associated with memory cells that are relatively close to the sense amplifiers may not be reliably sampled because the data may not be valid when the sampling control signal triggers the data sampling circuits.
For example, FIG. 1 is a schematic that illustrates a conventional semiconductor memory device that comprises memory cell array blocks 10-1, 10-2, . . . , and 10-8, multiplexers 12-1, 12-2, . . . , and 12-9, sense amplifiers 14-1, . . . , 14-4, and data sampling circuits 16-1, . . . , 16-4. In FIG.1, multiplexers 12-1, 12-2, . . . , and 12-9 are represented as MUX, sense amplifiers 14-1, . . . , and 14-4 as SA, and data sampling circuits 16-1, . . . , and 16-4 as DS.
In FIG.1, pairs of data input output lines IO11/B, IO12/B, IO13/B, and IO14/B for a memory cell array block 10-1 are arranged on the left and right of the memory cell array block 10-1. Pairs of data input/output line IO21/B, IO22/B, IO23/B, IO24/B, IO31/B, IO32/B, . . . , IO71/B, IO72/B, IO81/B, IO82/B, IO83/B, and IO84/B for the respective memory cell array blocks 10-2, . . . , and 10-8 are arranged on the left and right of the corresponding memory cell array block. The pairs of data input/output lines IO11/B, IO12/B, IO13/B, IO14/B, IO21/B, IO22/B, IO23/B, IO24/B, IO31/B, IO32/B, . . . , IO71/B, IO72/B, IO81/B, IO82/B, IO83/B, IO84/B for the respective memory cell array blocks 10-1, 10-2, . . . , and 10-8 are connected to four pairs of main data input output lines MIO1/B, MIO2/B, MIO3/B, MIO4/B. The semiconductor memory device further includes m word select signal lines, which are arranged vertically, for receiving the word select signals WL1, WL2, and WLm, and n column select signal lines, which are arranged horizontally, for receiving the column select signals CSL1, CSL2, . . . , and CSLn. The column select signals CSL1, CSL2, . . . , and CSLn are electrically coupled to corresponding input/output gates IOG.
Operations of the semiconductor memory device of FIG. 1 are described hereafter. A memory cell may be selected in one of the memory cell array blocks 10-1, 10-2, . . . , and 10-8 through activation of one of the word select signals WL1, WL2, . . . , and WLm and one of the column select signals CSL1, CSL2, . . . , and CSLn for writing data thereto or reading data therefrom. Multiplexers 12-1, 12-2, 12-3, . . . , 128, and 12-9 control the input/output of data between the pairs of data input/output lines IO11/B, . . . , and IO14/B and the pairs of main data input/output lines MIO1/B, and MIO4/B. For example, if a cell in memory cell array block 10-1 is selected, then multiplexers 12-1 and 12-2 are enabled and data are transmitted between the pairs of data input/output lines IO11/B, . . . , and IO14/B and the pairs of main data input/output lines MIO1/B, . . . , and MIO4/B. That is, during a write operation, data are input from the pairs of main data input/output lines MIO1/B, . . . , and MIO4/B to the pairs of data input/output lines IO11/B, . . . , and IO14/B. Conversely, during a read operation, data are transmitted from the pairs of data input/output lines IO11/B, and IO14/B to the pairs of main data input/output lines MIO1/B, . . . , and MIO4/B.
Although it is not shown, input and output of data is controlled in response to a read and write control signal and corresponding block select signals, which are applied to the multiplexers 12-1, 12-2, 12-3, . . . , 12-8, and 12-9. The sense amplifiers 14-1, . . . , and 14-4 amplify a difference in voltage between data signals on the main data input/output lines MIO1/B, . . . , and MIO4/B and then output the amplified signals as sense output signal pairs SIO1/B, . . . , and SIO4/B. The data sampling circuits 16-1, . . . , and 16-4 generate data output signals DO1, . . . , and DO4 in response to a sampling control signal FRP.
FIG. 2 illustrates a data sampling circuit of FIG. 1 in more detail. The data sampling circuit 16 comprises NAND gates NA1 and NA2, an inverter 11, a PMOS transistor P, and a NMOS transistor N, which are configured as shown. In FIG. 2, a sense output signal pair is represented as SIO and SIOB, and an output signal of the data sampling circuit 16 is represented as DO.
Operations of the data sampling circuit 16 of FIG. 2 are described hereafter. When the sampling control signal FRP is driven to a xe2x80x9clowxe2x80x9d logic level, both NAND gates NA1 and NA2 generate a xe2x80x9chighxe2x80x9d logic signal at output terminals thereof, regardless of the logic levels of the sense output signals SIO and SIOB. An inverter I1 generates an output signal at a xe2x80x9clowxe2x80x9d logic level. Therefore, both the PMOS transistor P and the NMOS transistor N are turned off.
When the sampling control signal FRP is driven to a xe2x80x9chighxe2x80x9d logic level and the sense output signals SIO and SIOB are at a xe2x80x9chighxe2x80x9d logic level and xe2x80x9clowxe2x80x9d logic level, respectively, the NAND gates NA1 and NA2 generate output signals at a xe2x80x9clowxe2x80x9d logic level and a xe2x80x9chighxe2x80x9d logic level, respectively. An inverter I1 generates an output signal at a xe2x80x9clowxe2x80x9d logic level. Therefore, the PMOS transistor P is turned on, the NMOS transistor N is turned off, and the data output signal DO is driven to a xe2x80x9chighxe2x80x9d logic level.
On the other hand, when the sampling control signal FRP is driven to a xe2x80x9chighxe2x80x9d logic level and the sense output signals SIO and SIOB are at a xe2x80x9clowxe2x80x9d logic level and xe2x80x9chighxe2x80x9d logic level, respectively, the NAND gates NA1 and NA2 generate output signals at a xe2x80x9chighxe2x80x9d logic level and a xe2x80x9clowxe2x80x9d logic level, respectively. An inverter I1 generates an output signal at a xe2x80x9chighxe2x80x9d logic level. Therefore, the PMOS transistor P is turned off, the NMOS transistor N is turned on, and the data output signal DO is driven to a xe2x80x9clowxe2x80x9d logic level.
FIGS. 3A and 3B are signal timing diagrams for the semiconductor device of FIG. 1. FIG. 3A illustrates an example in which a column address is decoded that results in the generation of column select signal CSL1. Similarly, FIG. 3B illustrates an example in which a column address is decoded that results in the generation of column select signal CSLn. The column address strobe latency is two cycles. That is, data is output from the semiconductor memory device two cycles after a column address strobe signal CAS has been input. The striped sections of FIGS. 3A and 3B indicate that the data is invalid during those periods.
In the first, second, and third cycles I, II, and III shown in FIGS. 3A and 3B, if an inverted write enable signal WEB at a xe2x80x9chighxe2x80x9d logic level is applied in a rising transition of a clock signal, then a read operation is performed. When a column address is input, the column select signal CSL1 is generated. A sense amplifier enable signal SAEN transitions to a xe2x80x9chighxe2x80x9d logic level in response to the xe2x80x9chighxe2x80x9d logic level of the inverted write enable signal WEB.
In the second and third cycles II and III of FIGS. 3A and 3B, sense amplifiers 14-1, . . . , and 14-4 amplify data, which are output from pairs of main data input/output lines MIO1/B, . . . , and MIO4/B, in response to a sense amplifier enable signal SAEN. The amplified data are then output as pairs of sense output signals SIO/B. Data sampling circuits 16-1, . . . , and 16-4 sample the pair of sense output signals SIO/B in response to a sampling control signal FRP to generate the data output signal DO.
As shown in FIGS. 3A and 3B with respect to the sense output signal pair SIO/B, data read from memory cells connected to the column select signal CSL1 are generated later than data read from memory cells connected to the column select signal CSLn. Furthermore, the sampling control signal FRP is driven to a xe2x80x9chighxe2x80x9d logic level at time t1, which corresponds to the time that the sense output signal pair SIO/B has valid data from the memory cells that are connected to the column select signal CSL1.
As the size of memory cell arrays increases, time t1 may be delayed even further, which may result in the loss of read data. Specifically, the enable period T1 for the sampling control signal FRP begins at time t1 and ends at time t2, which corresponds to the point in time at which the sense output signal pair SIO/B no longer has valid data from the memory cells that are connected to the column select signal CSLn. As time t1 approaches time t2, the enable period T1 (i.e., the period of time when there is valid data at the output of the sense amplifiers for data cells that are connected to the column select signal CSL1 and data cells that are connected to the column select signal CSLn) for the sampling control signal FRP shrinks. If the enable period T1 becomes too small or is eliminated entirely, then loss of read data may result.
Thus, an enable period of a sampling control signal of a conventional semiconductor memory device is generally limited as follows: The enable period of the sampling control signal begins when data read from memory cells that are relatively far from the sense amplifiers are provided at the output terminals of the sense amplifiers, and the enable period of the sampling control signal ends when data read from memory cells that are relatively close to the sense amplifiers are no longer valid at the output terminals of the sense amplifiers.
Unfortunately, during high frequency operation, read data from a memory cell array may be lost due to a short or potentially non-existent enable period for the sampling control signal. Consequently, there exists a need for improved semiconductor memory devices and methods for sampling data therefrom.
Embodiments of the present invention include semiconductor devices and methods of sampling data therefrom in which data is sampled from a memory cell array based on a relative position of a memory cell array section that contains the data. For example, a sense amplifier generates an output signal in response to an address of one or more cells in a memory cell array. A control circuit generates a sample control signal in response to at least a portion of the address (e.g., one or more high order bits of the address) of the one or more cells in the memory cell array. A data sampling circuit then samples the output signal of the sense amplifier in response to the sample control signal. The portion of the memory cell array address used to drive the control circuit may logically divide the memory cell array into two or more sections. The control circuit may adjust the timing of the sample control signal in accordance with the proximity of a memory cell array section to the sense amplifier. Advantageously, the present invention may be used to provide improved data sampling in memory cell arrays that may have non-negligible delays between the time that data are provided at the output of sense amplifiers from memory cell array sections that are closer to the sense amplifiers and the time that data are provided at the output of sense amplifiers from memory cell array sections that are further away from the sense amplifiers.
The address of the one or more cells in the memory cell array may be a column address, row address, or a combination of both a column address and a row address. Embodiments of the control circuit include a delay circuit, which generates a delayed control signal in response to a control signal, and logic circuitry, which generates the sample control signal in response to the control signal, delayed control signal, and the portion of the address of the one or more cells in the memory cell array. For example, if the portion of the address indicates that the one or more memory cell array cells are located in a section of the memory cell array that is relatively distant from the sense amplifier, then the logic circuitry may generate the sample control signal as the delayed control signal. If, however, the portion of the address indicates that the one or more memory cell array cells are located in a section of the memory cell that is relatively close to the sense amplifier, then the logic circuitry may generate the sample control signal as the control signal.
The control circuit may generate the sample control signal such that it is delayed relative to the control signal based on the proximity of the memory cell array section identified by the portion of the address of the one or more cells in the memory cell array. As a result, improved data sampling may be provided.